A memory device is often produced using a semiconductor fabrication process. In the current application, the term “semiconductor” will be understood to mean any semiconductor material, including but not limited to bulk semiconductive materials (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). Moreover, it shall be understood that a semiconductor device may comprise conductive and insulative materials as well as a semiconductive material. The result of a semiconductor process may be a die comprising memory circuitry, and it may be desirable to test that circuitry at some point during the process of constructing a memory device comprising that die. For instance, testing may occur while the die is part of a semiconductor wafer, after singulation from the wafer, during die packaging, or once the memory device (chip) is completed.
One conventional method of testing such a chip is to have an external testing device write data to every memory cell of the chip, then read data from every memory cell, and compare the input with the output. Such a comparison may reveal cells that failed to store the data properly. The addresses corresponding to these defective cells can be stored by the external testing device, and that stored data may be used to repair the chip. In order to effect such repair, redundant cells are provided on the chip, as well as at least one bank of programmable elements, such as fuses or anti-fuses, that controls access to the redundant cells. Assuming the bank to be comprised of anti-fuses, repair circuitry receives each address corresponding to a defective cell and, based on that address, blows at least one anti-fuse, thereby isolating the defective cell and associating the address with a redundant cell.
This error detect and repair scheme, however, raises issues. One such issue is the number of chips that may be tested at one time. A typical testing device is an AMBYX machine. The AMBYX can hold 256 chips and may electrically connect to all of them. Hence, the AMBYX can write to all chips in parallel. However, the AMBYX cannot read potentially differing data from all 256 chip in parallel. Rather, it has limited resources concerning reading data from the chips. Specifically, the AMBYX has only 64 terminals (known as “DQ's”) for reading from the chips. As a result, the 256 chips must share these DQ resources. Assuming each chip has only four DQ's of its own (in which case the chips would be known as a “x4” part), then the AMBYX could access only 16 chips at one time. Thus a typical testing process would involve writing data to cells of 16 chips; reading data from cells of all 16 chips; comparing the written data with the read data; and, for cells wherein the written data and read data do not match, storing the addresses of those failed cells. These steps must be performed 15 more times in order to test all 256 chips on the AMBYX. Moreover, once repaired, the chips are often retested in a second test cycle to determine whether the repair was successful, thereby requiring even more time, especially if the chips must be removed from the AMBYX for repair and then placed back onto the AMBYX for retesting. Further, more than one type of test is often conducted. As a result, there is a desire in the art to shorten test time.
Still other issues include the time and circuitry used to repair the chips. First, as mentioned above, the machine used to repair the chips may be different from the machine used to test the chips. Thus, it is often the case that the chips must be removed from the AMBYX and placed in another device, such as one made by TERADYNE, thereby undesirably adding time and effort. Further, maintaining the assumption (only for purposes of example) that completely packaged parts are being repaired, it can be understood that at least some of the redundant elements provided on a chip's die may have been used as a result of prior testing and repair processes, possibly including those accomplished at some stage prior to complete packaging. Thus, in repairing packaged parts, a testing or repair device may examine the chips to determine whether there are still redundant elements available for repair. If there are, the location of the elements is stored in registers within the testing device, and repair commences. Repair often involves transmitting in parallel the first address to the address inputs of one chip, transmitting a command to blow an anti-fuse on each chip that would reroute signals pertinent to that address to a redundant cell, and transmitting through the DQ lines a command to ignore the blow command if the first address does not match a failed address stored within the repair device's registers. This process is subsequently performed for the chip's second address, then the third address, etc., until all of the addresses have been accommodated. Then the process is repeated for the next chip. The serial nature of this repair scheme is very time consuming, and, as with the testing process, there is a desire in the art to reduce the time used for repair. Built In Self Repair (BISR) techniques may be used to affect test time, but often this is accomplished at the cost of the amount of die size needed to allot to on-chip registers and repair logic.
Moreover, neither alternative addresses the timing for the signals needed to blow the anti-fuses. In prior art, the appropriate signals must be transmitted to the chips for a certain amount of time to ensure that the anti-fuses will blow. Once that time has elapsed, the signals are changed to accommodate the next address. It is desirable to shorten repair time, but early reconfiguration of the signals to accommodate the next address risks an incomplete blow of the first anti-fuse and thereby may result in a failure to repair the chip. As a result, there is a need in the art for repair circuitry and methods that affect the time required to repair the chips while avoiding a great increase in die size and avoiding a great risk of an incomplete repair.